关于提高SoC设计时钟域交叉验证
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[1] N. Karimi and K. Chakrabarty, “Detection,Diagnosis, and Recovery from Clock-Domain Crossing Failures in Multi clock SoCs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 9, pp. 1395-1408, September 2013. [2] Y. Feng, Z. Zhou, D. Tong, X. Cheng, “Clock domain crossing fault model and coverage metric for validation of SoC design”, Proc. Design, Automation & Test in Eur. Conf. &Exhibition, Nice, France, pp. 1-6, 2007. [3] P. Ashar and V. Viswanath, “Closing the Verification Gap with Static Sign-off”, International Symposium on Quality Electronic Design, CA, USA, pp. 343-347, 2019. [4] C. Szàsz, and R. Şinca, “The Nontrivial Problem of Matching in Redundant Digital Systems”, Journal of Electrical and Electronics Engineering, vol. 12, no.1, pp. 51-56, May 2019. [5] S. Yang and M. Greenstreet, “Computing Synchronizer Failure Probabilities”, Proc. Design, Automation & Test in Europe Conf. & Exhibition, Nice, France, pp. 1-6, 2007. [6] I.W. Jones, S. Yang, and M. Greenstreet, “Synchronizer Behavior and Analysis”, Int’l Symp. on Asynchronous Circuits and Systems, NC, USA, pp. 117-126, 2009. [7] K. R. Talupuru and S. Athi, “Achieving Glitch- Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking”, 12th Intl. Workshop on Microprocessor Test and Verification, Austin, pp.5-9, 2011. [8] Y.Peng, I.W. Jones and M. Greenstreet, “Finding Glitches Using Formal Methods”, Intl. Symp. on Asynchronous Circuits and Systems, pp. 45-46, 2016. [9] T. Kapschitz and R. Ginosar, “Formal verification of synchronizers”, Proc. 13th IFIP Correct Hardware Design and Verification Methods, Germany, pp. 359-362, Oct 2005. [10] R. Dobkin, T. Kapshitz, S. Flur and R.Ginosar, “Assertion Based Verification of Multiple-Clock GALS Systems”, Proc. IFIP/IEEE Int. Conference on Very Large- Scale Integration (VLSI-SoC), Greece, pp. 1-6, Oct. 2008. [11] E. Clarke, D. Kroening, and K. Yorav, “Specifying and Verifying Systems with Multiple clocks”, P roc. Intl. Conf. on Computer Design, CA, USA, pp. 48-55, 2003. [12] G.Tarawneh, A.Yakovlev, and T.Mak, “Eliminating Synchronization Latency Using Sequenced Latching”, IEEE Transactions on Very Large-Scale Integration Systems, vol.22, no.2, pp.408–419, 2014. [13] S.Beer, J. Cox, R. Ginosar, T. Chaney, and D. M. Zar, “Variability in Multistage Synchronizers”, IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 12, pp. 2957–2969, 2015. [14] S. Beer and R. Ginosar, “Eleven Ways to Boost Your Synchronizer”, IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 6, pp. 1040–1049, 2015. [15] G. M. Brown, “Verification of a Data Synchronization Circuit for All Time”, Intl. Conf. on Application of Concurrency to Sys. Design, Finland, pp. 217-228, 2006. [16] A. Smrcka, V. Rehak, T. Vojnar, D. Safranek, P. Matousek, and Z. Rehak, “ Verifying VHDL Design with Multiple Clocksin SMV”, FMICS, , pp. 148-164, 2007. [17] A. Smrcka, “Verification of Asynchronous and Parametrized Hardware Designs”, Information Sciences and Technologies Bulletin of the ACM Slovakia, vol. 2, no. 2, pp. 60-69, 2010. [18] R. Ginosar, “Metastability and Synchronizer: ATutorial”, IEEE Design and Test of Computers, pp. 23-35, Oct. 2011. [19] C. Portmann, and T. Meng, “Metastability in CMOS library elements in reduced supply and technology scaled applications”, IEEE Journal of Solid-State Circuits, vol. 30, no. 1, pp. 39-46, 1995. [20] J. Reiher, M. Greenstreet, I. W. Jones, “ Explaining Metastability in Real Synchronizers”, Intl. Symp. on Asynchronous Circuits and Systems, Austria, pp. 59-67, 2018. [21] M. Thakur, B. B. Soni, P. Gaur and P. Yadav, “Analysis of metastability performance in digital circuits on flip-flop”, International Conference on Communication and Network Technologies, Sivakasi, India, pp. 265-269, 2014.
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